The present disclosure relates to an internal voltage generation circuit and, more particularly, to a threshold voltage control circuit capable of controlling a current drivability of an internal voltage driver and a stable internal voltage generation circuit using the same.
Generally, a semiconductor memory device uses a power supply voltage VDD and a ground voltage VSS in order to generate an internal voltage which is necessary for an internal circuit operation. The voltages required to operate the internal circuit of the semiconductor memory device can be classified into a core voltage VCORE which is supplied to a memory core region, a high voltage VPP which is used for driving a word line or used for overdriving and a back bias voltage VBB which is supplied to a bulk in which an NMOS transistor is provided in the memory core region.
Here, the core voltage VCORE is created by a voltage drop of the power supply voltage VDD to a predetermined level. However, since the high voltage VPP is higher than the power supply voltage VDD and the back bias voltage VBB is lower than the power supply voltage VDD, a charge pumping circuit is needed to create the high voltage VPP and the back bias voltage VBB.
FIG. 1 is a diagram illustrating a conventional core voltage generating circuit.
As shown in FIG. 1, the conventional core voltage generating circuit drives the core voltage VCORE in response to an enable signal LDVDL which is activated when a bank is enabled. That is, when the bank is enabled, the enable signal LDVDL is at a high level so that an NMOS transistor N16 in a comparator 12 is turned on and a PMOS transistor P14 in an internal voltage driver 14 is turned off. If the NMOS transistor N16 is turned on, the comparator 12 is enabled so that a division signal VA and a reference voltage VREFC are differentially amplified to generate a driving signal VB. At this time, the core voltage VCORE is divided to generate the division signal VA of a division signal generating unit 10. The level of the driving signal VB output from Node nd12 becomes low since an NMOS transistor N12 is more turned on than an NMOS transistor N14 when the division signal VA is lower than the reference voltage VREFC. The driving signal VB of a low level turns on a PMOS transistor P15 to drive the core voltage VCORE by supplying the power supply voltage VDD. The driving of the core voltage VCORE is continued until the level of the division signal VA is the same as that of the reference voltage VREFC.
The current drivability of the PMOS transistor P15, which operates as a driver for driving the core voltage VCORE, deteriorates when the level of the power supply voltage VDD is low. Thus, the core voltage VCORE is not driven to a desired voltage level when the power supply voltage VDD is at a low level. Therefore, a low-threshold voltage transistor is employed to prevent the drivability of the PMOS transistor P15 from being reduced when the power supply voltage VDD is in a low.
The driver using the transistor having a low-threshold voltage has an advantage in that a current drivability can be increased, but has a disadvantage in that a leakage current can be caused. That is, although the core voltage VCORE is driven to a desired voltage level so that the transistor included in the driver is turned off, a leakage current flows from the power supply voltage VDD to the core voltage VCORE because the threshold voltage of the turned-off transistor is low. The leakage current raises the level of the core voltage VCORE to a level exceeding the desired voltage level.